Junior DV and FPGA Prototyping Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help innovative companies unleash their potential through R&D and engineering services.

Your Role

• Study AMD Vivado and Vitis IDE.
• Model image and audio processing algorithms in Python and implement them in SystemVerilog RTL.
• Build FPGA environments and debug RTL designs using the Zybo Z7 board.
• Build SystemVerilog-based verification environments for RTL designs such as FIFO and UART.
• Learn SystemVerilog OOP concepts, constrained randomization, functional coverage, and assertions.
• Study the UVM methodology and wrap SystemVerilog environments into UVM.
• Use Shell and Python scripting.

Mandatory Qualifications

• Bachelor’s or Master’s degree in Electronics or a related field.
• Good understanding of digital logic design basics.
• Basic knowledge of IC design and verification using SystemVerilog.
• Beginner experience with EDA tools such as AMD Vivado, Intel Quartus, Cadence, Synopsys, or similar.
• Understanding of OOP concepts.
• Beginner-level English or higher.

Optional Qualifications

• FPGA design using HDL or a schematics editor.
• CPU architecture knowledge or embedded software development experience.
• Scripting using Bash, Python, TCL, or similar tools.

Capgemini is a global business and technology transformation partner with 340,000 team members in more than 50 countries.