Senior Physical Design Engineer

Your role

• Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below).
• Deep expertise in floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, scan re-ordering, placement, CTS, place and route.
• Cover all relevant activities related to timing analysis, including closure through sign-off, SI/noise, and ECO tasks for both functional and timing changes.
• In charge of validation and qualification tasks, including Formal Verification, EM/IR, DRC, LVS, Antenna, and ERC analysis and fixes.
• Be part of the overall Low Power solution development and implementation.
• Develop and enhance timing-related scripts for clock skew analysis, critical path analysis, various IO interfaces, and constraints partitioning/budgeting from toplevel to block level.
• Complete multiple design cycles of high complexity with little supervision.

Desired qualifications and skills

• 8+ years in challenging RTL2GDSII work on 10nm or below nodes with 500k–1 million+ instances in designs.
• Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence.
• Good knowledge of synthesis flow, insertDFT scan/coverage, and optimization.
• Excellent floorplan, power plan, CTS, place, route, and timing closure skills.
• Proficiency using Perl, TCL, Python scripting, and Makefile.
• Expertise in timing STA/PTSI, signal integrity closure, and ECO generation/implementation.
• Excellent EM/IR, DRC, LVS, and ERC analysis and fixing skills.
• Experience with sign-off tape-out closure work.
• Top-level floor planning, pin assignment, and tape-out activities are a plus.

We offer

• Competitive salary and benefits.
• Respect for your private life and your choices.
• All tools required for high performance in your field.
• Responsible approach, long-term commitments, and stability.