Senior DfT Engineer

Job Description

Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is a multi-disciplinary field of growing complexity which involves cooperation among multiple VLSI engineering skills, including design, architecture, verification, backend, timing, test, ATE and reliability and more.

Take the opportunity and join us as a Senior DFT Engineer.

Your role

• DFT implementation inline with existing test methodology for advanced process nodes
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST
• Closely work with the physical design team to resolve timing constraints and issues
• Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues
• Debug and improve important DFT KPIs: test coverage and pattern efficiency
• Hierarchical retargeting
• Silicon bring-up, diagnosis and support for physical failure analysis

Desired qualifications/skills

• 6+ years of hands-on experience with DFT and test flows using commercial EDA tools for large and complex SoCs
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard and MBIST/LBIST
• Experience with one of the main EDA providers: Synopsys DFT Compiler, Tetramax, VCS, Tessent and Modus/Encounter tool suite
• Experience in RTL simulation, synthesis, linting, CDC and RDC checks, STA, DFT and quality metrics is a plus
• Hands-on experience with Perl, Tcl or Python scripting
• Excellent analytical and problem-solving skills