Middle RTL Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help innovative companies develop their potential through R&D and engineering services.

Job Description

• Implement designs and microarchitecture at RTL level for high-performance blocks based on functional specifications from senior engineers and architects.
• Perform RTL debugging, ensuring design correctness and efficiency.
• Run and analyze lint and CDC (Clock Domain Crossing) checks.
• Collaborate with verification, physical design, and architecture teams.
• Contribute to front-end synthesis and optimization.
• Work on SoC-level integration and design.
• Apply power optimization techniques for energy-efficient designs.

What You Bring

• 3+ years of hands-on experience in digital design.
• Willingness to learn from senior colleagues.
• Strong knowledge of Verilog and/or VHDL for synthesis.
• Familiarity with SystemVerilog is a plus.
• Experience with Cadence Genus, Synopsys Design Compiler, or Fusion Compiler is a plus.
• Proven experience in RTL design, microarchitecture development, and functional specifications.
• Basic understanding of linting tools, CDC methodologies, and debugging flows.
• Familiarity with synthesis tools and SoC design is a strong plus.
• Bachelor's degree in EE, ECE, CE, CS, or a related field required; an MS or PhD is highly desired.
• Good communication and collaboration skills.

What You Will Have Working Here

• Health insurance from the first days, regardless of the probationary period.
• Company Christmas holidays from December 25 to December 31.
• Support for psychological rehabilitation and counseling through Superhumans Center and Veteran HUB.